What is instruction pipelining?

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written 7.7 years ago by

teamques10 ★ 64k

A typical instruction cycle can be divided into many sub cycles like Fetch instruction, Decode instruction, Execute and Store. The instruction cycle and the corresponding sub cycles are performed for each instruction. These sub cycles for different instructions can thus be interleaved or in other words these sub cycles of many instructions can be carried out simultaneously, resulting in reduced overall execution time. This is called instruction pipelining.
As mentioned above, to effectively apply pipelining to the process of instruction execution, the instruction cycle must be divided into following phases or sub cycles:

i) Fetch instruction (F): In this phase, the CPU reads the next instruction from the memory.

ii) Decode instruction (D): The instruction fetched in the previous phase is decoded and interpreted any data operand(s) if needed can also be fetched by the CPU at this time.

iii) Execute (E): The decoded instructions are finally executed by the CPU.

iv) Store(S): The result obtained as a result can then be stored back to the memory. This marks the end of the current instruction cycle.
Here instruction processing is divided into four stages. Hence it is also called four stage instruction pipelining. If the instruction cycle is divided into more phases, more pipelining can be achieved. Thus more efficient execution is also possible.
When there is no pipelining, a typical processor would take 12 clock cycles to execute three instructions (Assuming that each sub cycle takes one clock cycle to complete).
However when a pipelining is used, three instructions would be executed in 6 clock cycles as shown in Figure 5

In the third clock cycle, the decoding phase of the second instruction is done simultaneously with the fetching of the third instruction and execution of the first instruction. Similar interleaving of sub cycles occurs at all clock cycles except the first and the last one. This is responsible for speeding up the entire process.
In this case, the processor hardware needs to be divided into four independent functional units so that the fetch, decode, execute and store phases could be done simultaneously. The need for separate hardware units is sometimes considered.
The pipeline works normally only if there are no branch instructions and no interrupts occur. In case of branch instructions or interrupts, the pipeline is flushed. Thus making the pipelining useless.

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