written 7.7 years ago by | • modified 7.7 years ago |
Mumbai University > Computer Engineering > Sem-5 > Microprocessor
Marks: 5
Year: 2016
written 7.7 years ago by | • modified 7.7 years ago |
Mumbai University > Computer Engineering > Sem-5 > Microprocessor
Marks: 5
Year: 2016
written 7.7 years ago by |
General Purpose Register:
General Purpose Registers are also called as Working Data Registers.
It includes Integer Unit’s ‘r’ registers & Floating Point Unit’s ‘f’ registers.
Integer Unit Control/Status Register:
It includes:
I) Processor State Register (PSR):
It is 32 it register.
It contains various fields that control and hold status information.
The privileged instructions RDPSR & WRPSR are used to read & write the PSR respectively.
II) Window Invalid Mask (WIM):
WIM register works with the register windowing mechanisms of the Sun SPARC Processor.
It is used to determine a window overflow or underflow has taken place.
III) Trap Base Register (TBR):
This register contains 3 fields that determines the address to which the control is to be transferred in case of occurrence of trap.
The TBR can be written by the instruction WRTBR.
IV) Multiple/Divide Register (Y):
It is 32 bit register.
It contains most significant word of the double precision product of an integer multiplication & double precision dividend for an integer divide instruction.
V) Program Counter (PC, nPC):
It is 32 bit register.
PC contains the address of the instruction currently being executed by the Integer Unit.
nPC holds the address of the next instruction to be executed.
VI) Ancillary State Register (ASR):
SPARC provides 31 Ancillary Registers.
ASR’s numbered from 1 to 15 are reserved for future use by the architecture and should not be referenced by software.
ASR’s numbered from 16 to 31 are available for implementation-dependent uses such as timers, counters, diagnostic registers, self-test registers and trap-control register.
VII) IU Deferred-Trap Queue:
The contents and operation of an IU Deferred-Trap Queue are implementation dependent and are not visible to user application programs.
Floating Point Unit Control/Status Register:
I) FPU ‘f’ Register:
It is 32 bit register.
A single ‘f’ register can hold one single-precision operand.
II) Floating Point State Register (FSR):
FSR register field contain FPU Mode and Status Information.
The FSR is read and written by the STFSR & LDFSR.
III) Floating Point Deferred Trap Queue (FQ):
Floating Point Deferred Trap Queue, if present in implementation, contains sufficient state information to implement resumable, deferred floating point traps.
If floating point instructions execute synchronously with integer instructions, provision of a floating point queue is optional.
Co-Processor Control/Status Register:
All of the co-processor data and control/status registers are optional.
Co-processor Control/Status Registers are implementation-dependent & there structures are not fixed.
It includes:
a. Implementation-Dependent Coprocessor State Register (CSR).
b. Implementation-Dependent Coprocessor Deferred Trap Queue (CQ).
These registers are accessed via load/store coprocessor and CPop1/CPop2 format instructions.