Question Paper: Digital Logic Design & Analysis : Question Paper Dec 2015 - Computer Engineering (Semester 3) | Mumbai University (MU)
0

Digital Logic Design & Analysis - Dec 2015

Computer Engineering (Semester 3)

TOTAL MARKS: 80
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks.
1 (a) Convert decimal number 199.375 into binary, octal. hexadecimal system.(2 marks) 1 (b) Perform hexadecimal arithmetic operation: DADA+BABA.(2 marks) 1 (c) Convert binary data 1010 into 7 bit even parity hamming code.(2 marks) 1 (d) Express the equation in standard POS form: F(A,B,C)=∑m (0, 2, 5, 7).(2 marks) 1 (e) Differentiate in brief between combinational & sequential circuits.(2 marks) 1 (f) Compare TTl & CMOS with respect to speed, power dissipation, fan-In & fan-out.(2 marks) 1 (g) Explain in brief weighted & non-weighted codes with one example each.(2 marks) 1 (h) Explain the race around condition in jk flip-flop. State various methods to overcome it.(2 marks) 1 (i) Convert JK flip-flop into D-flip-flop & T-flip-flop (show only the design without steps).(2 marks) 1 (j) What is Modulus of the counter? For MOD-6 counter how many flip-flops are needed?(2 marks) 2 (a) Simplify the following equation using K-map to obtain minimum POS equation & realize the minimum equation using only NOR gates.
F(A, B, C, D)= μm (1, 3, 4, 6, 9, 11, 12, 14).
(10 marks)
2 (b) What is multiplexer tree? Construct 32:1 multiplexer using 8:1 multiplexer only. Explain how the logic on particular data line is steered to the output in this design with example.(10 marks) 3 (a) Reduce using Quine McClusky method & realize the equation using only NAND gates.
F(P,Q,R,S)=∑m(0, 1, 2, 8, 10, 11, 14, 15).
(10 marks)
3 (b) Implement single digit BCD adder using 4 bit binary adder IC 7483, Show the design procedure & explain its operation.(10 marks) 4 (a) Explain the concept of comparator. Develop the truth table for 2-bit binary comparator & design it using a suitable decoder & additional gates.(10 marks) 4 (b) Design MOD-5 synchronous up-counter using JK flip-flops with all the design steps.(10 marks) 5 (a) Input to a combinational circuit is a 4-bit binary number. Design the circuit with minimum hardware for the following:
-output p=1 if the number is prime.
- output Q=1 if the number is divisible by 3.
(10 marks)
5 (b) Draw a circuit diagram for 3-bit asynchronous binary down counter using master-slave JK flip-flops. Show the output of each flip-flop with reference to the clock & justify that the down counting action. Also prove from the timing diagram that the counters is "divide by 8" counter.(10 marks) 6 (a) What is shift register? Explain 4-bit bidirectional shift register.(10 marks) 6 (b) Draw & explain the working of 4-bit ring counter with timing diagram,(10 marks)

Please log in to add an answer.