Question Paper: Digital Logic Design & Analysis : Question Paper May 2015 - Computer Engineering (Semester 3) | Mumbai University (MU)
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Digital Logic Design & Analysis - May 2015

Computer Engineering (Semester 3)

TOTAL MARKS: 80
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks.

1 (b) Represent (5210 into Excess-3 code and Gray code. (2 marks)

1 (c) Find the one's complement and two's complement of (57)10. (2 marks)

1 (d) Realize y=AB+AB using NAND gates only. (2 marks)

1 (e) Obtain hamming code for 1011. (2 marks)

1 (f) Convert (126)10 to Octal, Hexcode. (2 marks)

1 (g) State demorgans law. (2 marks)

1 (h) Convert (214.32)10 to binary. (2 marks)

1 (i) Perform binary subtraction using 2's complement for (62)10 and (99)10. (4 marks)

2 (a) Minimize the logic functon using Quine-McCluskey method.
f(A, B, C, D)=∑m(1, 3, 7, 9, 10, 11, 13, 15).
(12 marks)

2 (b) Implement the following expression using single 4:1 Mux.
f=(A, B, C, D)= ∑m (0, 1, 2, 4, 6, 9, 12, 14).
(8 marks)

3 (a) Design a 4-minute (A, B, C, D) digital circuit that will give at its output (X) a logic 1 only if the binary number at the input is between 2 and 9 (including). (10 marks)

3 (b) Simplify $$Y = \overline {(A + \overline A B ) (C+ \overline D)}$$ (5 marks)

3 (c) Design 1 bit comparator using logic gates. (5 marks)

4 (a) Given the logic expression $$A + \overline {BC} + AB\overline {D} + ABCD$$
i) Express on standard SOP
ii) Draw K-map for the equation.
iii) Minimize and realize using NAND gates only.
(12 marks)

4 (b) Design 8 bit BCD adder. (8 marks)

5 (a) Design an mod-5 synchronous up counter using JK FF. (10 marks)

5 (b) Convert SR FF to TFF and JK FF. (10 marks)

Write short note on (any three):

6 (a) VHDL. (7 marks)

6 (b) Multivibrators (7 marks)

6 (c) Gray code & Excess - 3 code(7 marks)

6 (d) Johnson Ring Counter. (7 marks)

1 (a) Convert (121.2)3 into base 10. (2 marks)