Question Paper: Digital Logic Design & Analysis : Question Paper May 2014 - Computer Engineering (Semester 3) | Mumbai University (MU)
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Digital Logic Design & Analysis - May 2014

Computer Engineering (Semester 3)

TOTAL MARKS: 80
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks.
1 (a) Perform following without converting into other bases.
(i) (57)8 x (24)8
(ii) (312.0)4 + (213.2)4
(5 marks)
1 (b) Define following Parameter for CMOS family :-
(i) Fan out (ii) Fan in
(5 marks)
1 (c) Design a full adder using half adder and additional gates.(5 marks) 1 (d) Explain concept of bistable multivibrators.(5 marks) 2 (a) Using Quine MC Clusky method determine minimal SOP form for :-
F(A, B, C, D) = ?m(1, 2, 3, 6, 7, 10, 12, 14)
(10 marks)
2 (b) Obtain even Parity hamming code for 1010. prove that hamming code is an error detecting and correcting code.(10 marks) 3 (a) Explain the operation of 4-bit universal shift register.(10 marks) 3 (b) Design a 2-bit digital comparator that accept inputs A and B and gives three outputs. G,E and L.
(i) Output G, when A<B
(ii) Output E, when A=B
(iii) Output L, when A>B
(10 marks)
4 (a) Implement the following using 8:1 Mux
F(A, B, C, D) =πm(1, 3, 5, 9, 11, 12, 13)
(10 marks)
4 (b) Simplify following function using k-map.
F(A, B, C, D) = ��‘m(1, 2, 3, 4, 6, 8, 10, 14, 15)
(10 marks)
5 (a) Design a sequence generator for following sequence. Identify and check for lock out condition 0→3→5→6→0.(10 marks) 5 (b) Explain 4-bit johnson conuter. Draw its timing diagram.(10 marks)


Attempt any two :-

6 (a) Working of Master-Slave J-K flip flop.(10 marks) 6 (b) Details and comparison of FPGA and CPLD.(10 marks) 6 (c) Convert the following :-
(i) SR to JK
(ii) SR to D
(iii) JK to D
(iv) JK to SR.
(10 marks)

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