Question Paper: Digital Logic Design & Analysis : Question Paper Dec 2013 - Computer Engineering (Semester 3) | Mumbai University (MU)
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## Digital Logic Design & Analysis - Dec 2013

### Computer Engineering (Semester 3)

TOTAL MARKS: 80
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks.
1 (a) State De-morgan's Theorems. Convert the following (761.514)8 to binary and hexadecimal (5 marks) 1 (b) Subtract the following using method given below :
(i) (11)10 - (22)10 using 2's complement.
(ii) (33)10 - (44)10 using one's complement.
(5 marks)
1 (c) Write short note on Ring Counter using 'D' FF.(5 marks) 1 (d) Compare FPGA and CPLD(5 marks) 2 (a) Perform the following directly without converting to any other base.
(i) (63)8 x (21)8
(ii) (D9)H - (80)H
(5 marks)
2 (b) (i) Simplify the Boolean expression
$$Y=?\bar{A}BC+A\bar{B}C+AB\bar{C}+ABC$$
(ii) Express it is standard POS Form
$$Y=(A+B)(A+C)(B+\bar{C})$$
(5 marks)
2 (c) Simplify the logic function using k-map
f(A, B, C, D)= ��‘m(4, 5, 6, 7, 8, 10, 12) d(2, 9, 11)
Draw the logic diagram using NAND gates only.
(5 marks)
2 (d) Explain Astable multivibrator using op-amp with neat waveforms.(5 marks) 3 (a) Design a sequence generator to generate the sequence using 'D' FF 1101001 and repeat. Draw neat state diagram and ckt diagram.(10 marks) 3 (b) Implement the following logic function using all 4:1 multiplexer with select inputs as 'B', 'C', 'D', 'E' only
F(A, B, C, D, E) = ?m(0, 1, 2, 3, 6, 8, 9, 10, 13, 15, 17, 20, 24, 30)
(10 marks)
4 (a) Explain 3 bit Bidirectional shift register using JK Flip Flop. Draw the neat waveforms.(10 marks) 4 (b) What is FPGA. Explain basic architecture. What are its advantages over CPLD.(10 marks) 5 (a) Design Full adder using 3:8 decoder with active low outputs and NAND gates.(5 marks) 5 (b) Use Quine Mc-Cluskey method to simplify the logic function as given below.
F(A, B, C, D, E) = ?m(0, 1, 8, 10, 11, 12, 20, 21, 30) + d(14, 19) Realize the above function using NAND gates.
(15 marks)
6 (a) Design mod-10 synchronous counter using JK Flip Flops. Check for the lock out condition. If so, how the lock out condition can be avoided? Draw the neat state diagram and circuit diagram with Flip Flops.(15 marks) 6 (b) Explain the transfer characteristics of TTL NAND gate and hence define Fan-in and Fan out.(5 marks)

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