Question Paper: Digital Logic Design & Analysis : Question Paper Dec 2012 - Computer Engineering (Semester 3) | Mumbai University (MU)
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Digital Logic Design & Analysis - Dec 2012

Computer Engineering (Semester 3)

TOTAL MARKS: 80
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks.
1(a) Using Quine McCluskey method, determine the minimal SOP for-F(A,B,C,D)= ? m(4,5,8,9,11,12,13,15).(10 marks) 1(b) Obtain hamming code for 1010. Prove that hamming code is an error detecting and correcting code.(10 marks) 2(a) Implement the following using 8: I MUXF (A, B, C, D) = ? m (O, 1, 2, 4, 6, 7, 8, 10, 14, 15)(10 marks) 2(b) Draw a 4 bit ring counter. Draw the timing diagram and explain the working of counter.(10 marks) 3(a) Design a sequence generator using T flip flop for the given sequence. Also identify and check for lock-out condition (if any)
0 ? 2 ? 4 ? 5 ? 0
(10 marks)
3(b) Using k-map method of minimization technique simplifyF (A, B, C, D) = ? M (1, 2, 3, 8, 9, 10, 11, 14) + d (7, 15)(10 marks) 4(a) Explain the operation of a 4 bit universal shift register. (10 marks) 4(b) Design a full adder circuit using half adders and some gates.(10 marks) 5(a) Convert: SR to JK flip-flop and SR to D flip-flop.(10 marks) 5(b) Compare the different logic families with respect to the following parameters - Fan in, Fan out, Noise margin, speed and power dissipation.(10 marks) 6(a) Convert (243.63)8 to decimal, binary (210.2)4 + (312.2)4(10 marks) 6(b) Draw and design a combinational circuit that multiplies two 2-bit numbers A1 A2 and B1 B2 to produce a 4 bit product C3 C2 C1 CO. (10 marks) 7(a) DeMorgan's Theorem:(5 marks) 7(b) Decade Counters:(5 marks) 7(c ) Race around condition in JK flip-flop:(5 marks) 7(d) PLA and PAL: (5 marks)

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