Question Paper: Digital Electronics : Question Paper Dec 2015 - Electronics & Telecomm. (Semester 3) | Mumbai University (MU)
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Digital Electronics - Dec 2015

Electronics & Telecomm. (Semester 3)

TOTAL MARKS: 80
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks.
1 (a) Compare SRAM and DRAM(5 marks) 1 (b) Compare Mealy and Moore machine.(5 marks) 1 (c) Compare TTL and CMOS Logic(5 marks) 1 (d) Design a full adder using 3:8 decoder.(5 marks) 2 (a) State and Prove DeMorgan's Laws.(10 marks) 2 (b) Explain carry look ahead adder. What is its advantages over a simple adder.(10 marks) 3 (a) Design a 4bit Grey to Binary code converter.(10 marks) 3 (b) Implement the given function using 8:1 Multiplexer F(A, B, C, D)=∑(0,1,4,5,6,8,10,12,13).(10 marks) 4 (a) Explain the working of Bidirectional Shift register with proper timing diagram.(10 marks) 4 (b) Write a VHDL program to design a 1:8 Demux using Data flow modeling.(10 marks) 5 (a) Minimize the following expression using Quine McClusky Technique F(A, B, C, D)= ∑m(1,2,5,7,9,15)+d(0,3,11)(10 marks) 5 (b) Convert D FF to T FF and SR FF to JK FF.(10 marks) 6 (a) Design synchronous counter to count the sequence 0-1-2-3-4-5-0.(10 marks) 6 (b) Compare PAL with PLA with suitable examples of logic expressions.(10 marks)

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