Question Paper: Digital Electronics : Question Paper May 2015 - Electronics & Telecomm. (Semester 3) | Mumbai University (MU)
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Digital Electronics - May 2015

Electronics & Telecomm. (Semester 3)

TOTAL MARKS: 80
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks.
1 (a) Compare combinational logic circuits with sequential circuits.(5 marks) 1 (b) Compare PLA and PAL.(5 marks) 1 (c) Explain static RAM.(5 marks) 1 (d) Explain Master-Slave JK Flip Flop.(5 marks) 2 (a) State and prove laws of Boolean Algebra.(10 marks) 2 (b) Using Quine McCluskey method minimize the following
F[A,B,C,D]=πm(0,2,5,7,8,10,12,15).
(10 marks)
3 (a) Implement Full adder using 8:1 multiplexers.(10 marks) 3 (b) Write VHDL code for 3-bit up counter(10 marks) 4 (a) Design a two bit digital comparator and implement using basic logic gates.(10 marks) 4 (b) Draw a neat circuit of BCD adder using IC 7483.(10 marks) 5 (a) What is universal shift register? Explain any two modes of shift register.(10 marks) 5 (b) i) Convert a D FF to T FF
ii) Convert a JK FF to T FF
(10 marks)
6 (a) Design a Synchronous counter using T FF for the sequence given below:
1-2-3-4-5-6-7-1
(10 marks)
6 (b) Define the following terms for logic families
i) Propagation Delay
ii) Fan out
iii) Power Description
iv) Noise Margin
v) Fan in
(10 marks)

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