Digital Electronics - Dec 2014
Electronics & Telecomm. (Semester 3)
TOTAL MARKS: 80
TOTAL TIME: 3 HOURS (1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks. 1 (a) Compare Moore and Mealy machine models.(5 marks) 1 (b) Design a 4:1 multiplexer using only NAND gates.(5 marks) 1 (c) Write a VHDL code for full adder.(5 marks) 1 (d) Convert SR F/F to D F/F.(5 marks) 2 (a) Implement the following Boolean function with 8: multiplexer F(A,B,C,D)=?m(0,3,5,6,8,9,10,12,14).(10 marks) 2 (b) State truth table of 3 bit Gray to Binary conversion then design it using 3:8 decoder and additional gates.(10 marks) 3 (a) Use the quine McCluskey method of minimization and find the expression for the function.
F(A,B,C,D)=?m(0,1,2,3,5,7,8,9,11,14).(10 marks) 3 (b) Define the following in terms of Logical families
i) Propagation delay
iii) Power Dissipation
iv) Figure of Merit
v) Noise margin(10 marks) 4 (a) Design ripple counter using JK flip flop for the state: (10 marks) 4 (b) i) Give the advantage and disadvantage of CMOS family.
ii) Implement a full-subtractor using two-Half-Subtractors.(10 marks) 5 (a) Design an even parity generator with 3 data bits.(10 marks) 5 (b) Explain any one shift register in detail.(10 marks) 6 (a) Draw and explain the block diagram of architecture of XC9500 CPLD family.(10 marks) 6 (b) Explain Johnson counter or twisted ring counter.(10 marks)