Digital Electronics - May 2014

Electronics & Telecomm. (Semester 3)

TOTAL MARKS: 80
TOTAL TIME: 3 HOURS (1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks.

Explain the following

1 (a) For ECL and CMOS logic families define-
(i) noise margin (ii) fan-in (iii) fan-out(5 marks) 1 (b) Compare Asynchronous and synchronous counter(5 marks) 1 (c) Explain static RAM(5 marks) 1 (d) Explain Master-Slave J.K Flip-Flop(5 marks) 2 (a) Perform following operation using 2's compliment method-
(i) (28)₁₀-(42)₁₀ (ii) (52)₁₀-(-18)₁₀(5 marks) 2 (b) Prove the following using Boolean algebra
$$\bar{A}BC+A\bar{B}C+ABC+AB\bar{C}=AB+BC+CA$$(5 marks) 2 (c) Design 2 bit comparator(10 marks) 3 (a) Minimum the following using Quine Mc Clusky method
F(A,B,C,D)=Σm(3,4,9,13,14,15) + Σd(5,6)(10 marks) 3 (b) Design synchronous counter using J.K flip-flop for the given sequence- 0-2-3-5-7-0(10 marks) 4 (a) Design following Boolean equation using 4:1 mux
F(A,B,C,D)=Σ m(2,4,5,7,9,11,12) (5 marks) 4 (b) Compare EPROM and FLASH memories(5 marks) 4 (c) Explain bidirectional 4 bit universal shift register(10 marks) 5 (a) Explain 3:8 decoder(5 marks) 5 (b) Explain Mealey machine and Moore machine(5 marks) 5 (c) Write VHDL code for 3 bit binary down counter(10 marks) 6 (a) Explain Architecture and features of FPGA(10 marks) 6 (b) Implement X-OR gate using NAND(5 marks) 6 (c) Convert (118₁₀) in to (i) BCD (ii) Hexadecimal (iii) Octal(5 marks)