Question Paper: Digital Electronics : Question Paper Dec 2013 - Electronics & Telecomm. (Semester 3) | Mumbai University (MU)
0

Digital Electronics - Dec 2013

Electronics & Telecomm. (Semester 3)

TOTAL MARKS: 80
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks.
1 (a) Compare combinational circuit with sequential circuit(5 marks) 1 (b) Compare TTL with CMOS logic families(5 marks) 1 (c) Compare SRAM with DRAM(5 marks) 1 (d) Compare FPGAs with CPLDs(5 marks) 2 (a) State and prove De Morgan's theorem(10 marks) 2 (b) Using Quine McClusky method, minimize the following :
F(A,B,C,D,E)= Σm(0,1,3,7,8,9,11,15,22,24,27)+d(6,16)
(10 marks)
3 (a) Implement the following Boolean equations single 8:1 MUX and few logic gates:
F(A,B,C,D,E)=Σm(0,1,3,4,8,9,15)
(10 marks)
3 (b) Write (32)10 into its BCD code, and Ex3 code.(5 marks) 3 (c) Implement Y=A+BC using only NOR gate(5 marks) 4 (a) Draw a neat circuit of BCD adder using IC 7483 and explain(10 marks) 4 (b) It is desired to develop the circuit for controlling a lamp on a staircase between 1st and 2nd floor of a building. Each floor is having only one switch. If a lamp is made 'ON' using switch of 1st floor, one should be able to switch it 'OFF' using a switch of 2nd floor and vice versa. design the circuit for the same. write the VHDL code for the same.(10 marks) 5 (a) What is shift refister? Explain any one type of shift register. Give its application.(10 marks) 5 (b) Convert D type flip flop into T type flip flop (5 marks) 5 (c) Compare PAL with PLA(5 marks) 6 (a) Design a synchronous counter using D type flip flop for getting the following sequence : 0-2-4-6-0. take care of lockout condition.(10 marks) 6 (b) Explain any one application of Johnson counter(5 marks) 6 (c) Draw the block diagram of internal architecture of XC9500 family CPLD and explain in brief.(5 marks)

Please log in to add an answer.