Mumbai University > Computer Engineering > Sem 3 > Digital Logic Design and Analysis

Marks: 2M

Year: Dec 2015

Race around condition in JK flip-flop:

1. In JK flip flop as long as clock is high for the input conditions

2. J&K equals to the output changes or complements its output from 1–>0 and 0–>1.

3. This is called toggling output or uncontrolled changing or racing condition. Consider above J&K circuit diagram as long as clock is high and J&K=11 then two upper and lower AND gates are only triggered by the complementary outputs Q and Q(bar). I.e. in any condition according to the propagation delay one gate will be enabled and another gate is disabled.

4. If upper gate is disabled then it sets the output and in the next lower gate will be enabled which resets the flip flop output.

Steps to avoid racing condition in JK Flip flop:

1. If the Clock On or High time is less than the propagation delay of the flip flop then racing can be avoided. This is done by using edge triggering rather than level triggering.

2. If the flip flop is made to toggle over one clock period then racing can be avoided. This introduced the concept of Master Slave JK flip flop.