Question Paper: Digital Circuits and Design : Question Paper Dec 2014 - Electronics Engineering (Semester 3) | Mumbai University (MU)
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Digital Circuits and Design - Dec 2014

Electronics Engineering (Semester 3)

TOTAL MARKS: 80
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks.
1 (a) Interfacing between CMOS and TTL.(5 marks) 1 (b) Convert T flip-flop to D flip-flop.(5 marks) 1 (c) XC 4000 FPGA architecture block diagram.(5 marks) 1 (d) Draw truth table and logic diagram of Full subtractor(5 marks) 2 (a) Write a VHDL code for Full adder.(10 marks) 2 (b) Design MOD 10 asynchronous counter.(10 marks) 3 (a) Design a mealy sequence detector to detect �1010-- using D flip-flops and logic gates.(10 marks) 3 (b) Design a circuit with optimum utilization of PLA to implement the following functions
R=? m (0,2,5,7,11,12)
P=?m(1,3,8,9,11,13}
Q=?m(0,5,8,12,14)
(10 marks)
4 (a) Implement following function using 8:1 MUX and logic gates
P (X,Y,Z,W)=? m(0,3,4,7,8,9,13,14).
(10 marks)
4 (b) Eliminate redundant states and draw reduced state diagram
(10 marks)
5 (a) Use K-map to reduce following function and then implement it by NOR gates.
F=? M (0,3,4,5,8,10,12,14)+d(2,9)
(10 marks)
5 (b) Design 8 bit up counter using IC 74163, draw a circuit diagram and explain its working.(10 marks)


Write short notes any three:

6 (a) Noise Margins(7 marks) 6 (b) JTAG and BIST(7 marks) 6 (c) PAL and PLA(7 marks) 6 (d) Stuck at '0' and '1' faults.(7 marks)

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