Digital Electronics - Dec 2015
Electronics & Telecom Engineering (Semester 3)
TOTAL MARKS: 100
TOTAL TIME: 3 HOURS (1) Question 1 is compulsory.
(2) Attempt any four from the remaining questions.
(3) Assume data wherever required.
(4) Figures to the right indicate full marks.
Solve any one question from Q1 and Q2
1 (a) State the following characteristics of digital TTL and CMOS IC's:
i) Speed of operation
ii) Noise margin
iii) Figure of merit.(6 marks) 1 (b) Implement the following function using single 4:1 mux: F(A B C D)= ∑m (2, 4, 5, 7, 10, 14).(6 marks) 2 (a) Draw and explain the working of 2 input CMOS NAND gate.(6 marks) 2 (b) Design and implement full adder circuit using 3:8 decoder.(6 marks)
Solve any one question from Q3 and Q4
3 (a) Design and implement a synchronous up decade counter using D FF.(6 marks) 3 (b) Convert D to T and T to D FF.(6 marks) 4 (a) Compare Moore and Mealy circuit with suitable example.(6 marks) 4 (b) Design a circuit to generate sequence 0-2-5-4-7-3 using T FF.(6 marks)
Solve any one question from Q5 and Q6
5 (a) Compare between PROM, PAL, PLA.(5 marks) 5 (b) A combinational circuit is define by a function F1=∑m (1, 3, 5), F2=∑m(5, 6, 7). Implement the circuit with a PLA having 3 inputs, 3 product terms and two outputs.(8 marks) 6 (a) Compare between CPLD and FPGA.(5 marks) 6 (b) Draw a neat diagram of one cell of static and dynamic RAM with its working.(8 marks)
Solve any one question from Q7 and Q8
7 (a) What are different types of architecture in VHDL? Explain in detail.(7 marks) 7 (b) Write a VHDL code for binary to gray code converter.(6 marks) 8 (a) What is the difference between concurrent and sequential statement in VHDL. Explain with proper example.(7 marks) 8 (b) Write a VHDL code for D FF using synchronous reset input.(6 marks)