Digital Electronics & Logic Design - May 2014
Information Technology Engineering (Semester 3)
TOTAL MARKS: 100
TOTAL TIME: 3 HOURS (1) Question 1 is compulsory.
(2) Attempt any four from the remaining questions.
(3) Assume data wherever required.
(4) Figures to the right indicate full marks.
Answer any one question from Q1 and Q2
1 (a) State conditions to be satisfied for interfacing, by driving & load gate. Draw and explain the interfacing of CMOS driving TTL.(6 marks)
1 (b) Minimize the following functions using k-map and implement using basic logic gates f(A,B,C,D)= ∑m(0,1,2,4,8,9,12,13)+d(3,6,7).(6 marks)
2 (a) Convert the following Number into its equivalent Hexadecimal, Decimal & Binary Number (show step-by-step process of conversion):
i) (357.2)8 ii) (458.54)8(6 marks) 2 (b) Draw and explain the look ahead carry generator.(6 marks)
Answer any one question from Q3 and Q4
3 (a) Explain the difference between asynchronous and synchronous counter & Convert J-K flip flop into D-FF. Show the design.(6 marks) 3 (b) Draw an ASM chart of 2-bit up-down counter having mode control input.(6 marks) 4 (a) Draw and explain the behavior of M-S JK flip flop with waveform.(6 marks) 4 (b) Draw and explain Johnson counter with initial state ?1110?, from initial state explain all possible states.(6 marks)
Answer any one question from Q5 and Q6
5 (a) Explain the difference between CPLD and FPGA.(6 marks) 5 (b) What is meant by CPLD? Draw & Explain the block diagram of CPLD.(7 marks) 6 (a) Give the comparison between PROM, PLA and PAL.(6 marks) 6 (b) Design the full adder using PLA.(7 marks)
Answer any one question from Q7 and Q8
7 (a) Explain with example Dataflow and behavioural modelling styles used in VHDL programming.(6 marks) 7 (b) Explain with example 'signal' and 'variable' in VHDL.(7 marks) 8 (a) Define entity declaration for AND gate. Also write architecture of AND gate in structural & Data modelling styles.(6 marks) 8 (b) What is the difference between behavioural model and structural model in VHDL?(7 marks)