Question Paper: Digital Circuits and Design : Question Paper May 2016 - Electronics Engineering (Semester 3) | Mumbai University (MU)
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Digital Circuits and Design - May 2016

Electronics Engineering (Semester 3)

TOTAL MARKS: 80
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks.
1(a) Interfacing between CMOS and Ttl(5 marks) 1(b) Explain Shift Register and its applications(5 marks) 1(c) PLA and PAL(5 marks) 1(d) Draw truth table and logic diagram of Full Subtractor(55 marks) 2(a) Write a VHDL code for Full Adder(10 marks) 2(b) Design MOD 8 asynchronous counter.(10 marks) 3(a) Design a mealy sequence detector to detect ---0101--- using D flip-flops and logic gates(10 marks) 3(b) Design a circuit with optimum utilization of PLA to implement the following functions
F1 = ∑m (0, 2, 5, 8, 9, 11)
F2 = ∑m (1, 3, 8, 10, 13, 15)
F3 = ∑m (0, 1, 5, 7, 9, 12, 14)
(10 marks)
4(a) Implement folloeing function using 8:1 MUX and logic gates
P(A,B,C,D) = ∑m (1,2,6,7,8,10,13,14)
(10 marks)
4(b) Construct ring counter using IC 74194 and the output waveform(10 marks) 5(a) use K-map to reduce following function and then implement it by NOR gates.
F = πM (1, 2, 5, 8, 10, 12, 15) + d(0, 6)
(10 marks)
5(b) Design 6 bit up counter using IC 74163, draw a circuit diagram and explain its working.(10 marks)


Write short notes on any three

6(a) JTAG and BIST(7 marks) 6(b) Struck at '0' and '1' faults(7 marks) 6(c) XC 4000 FPGA architecture block diagram(7 marks) 6(d) Noise Margins.(7 marks)

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