Question Paper: Digital Electronics : Question Paper Dec 2016 - Electronics & Telecomm (Semester 3) | Mumbai University (MU)
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Digital Electronics - Dec 2016

Electronics & Telecomm. (Semester 3)

TOTAL MARKS: 80
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks.
1(a) State basic theorems of Boolean algebra.(5 marks) 1(b) Compare Mealy and Moore machine.(5 marks) 1(c) Define Noise Margin,
Propagation delay,
Power Dissipation
(5 marks)
1(d) Design a full adder using half adders and logic Gates(5 marks) 2(a) Prove that NAND and NOR Gates are universal Gates.(10 marks) 2(b) Design a 2-bit comparator and implement using logic Gates.(10 marks) 3(a) Design a 4 bit Binary to Grey code converter.(10 marks) 3(b) Implement the given function using single 4:1 Multiplexer and few logic gates: F (A,
B,
C,
D) = ∑m(0,
1,
4,
5,
6,
8,
9,
10,
12,
13,
15)
(10 marks)
4(a) What is a universal shift register? Explain its various modes of operations(10 marks) 4(b) Write a VDHL program to design a 3:8 Decoder.(10 marks) 5(a) Minimize the following expression using Quine MeClusky Technique. F(A,
B,
C,
D) = ∑m(0,
1,
2,
3,
5,
7,
9,
11)
(10 marks)
5(b) Convert JK FF to T FF and JK FF to D FF(10 marks) 6(a) Explain the working of 3-bit asynchronous counter with proper timing diagram.(10 marks) 6(b) Write a note on CPLDs.(10 marks)

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written 17 months ago by gravatar for Team Ques10 Team Ques10 ♦♦ 400
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