Question Paper: Basic VLSI Design : Question Paper Dec 2015 - Electronics Engineering (Semester 6) | Mumbai University (MU)
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Basic VLSI Design - Dec 2015

Electronics Engineering (Semester 6)

TOTAL MARKS: 80
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks.
1 (a) Draw CMOS implementation of D Flip Flop.(5 marks) 1 (b) Implement y=A+B-C using dynamic CMOS logic.(5 marks) 1 (c) Explain latchup in CMOS inverter.(5 marks) 1 (d) Define scaling. Explain significance of scaling in VLSI circuits.(5 marks) 2 (a) Draw CLA (carry lookahead adder) carry chain using
i) Static CMOS logic
ii) Dynamic CMOS logic
Pseudo NMOS logic.
(10 marks)
2 (b) Draw IT DRAM cell and explain it's read write and refresh operation.(10 marks) 3 (a) Explain clock generation networks and distribution networks used in VLSI circuits.(10 marks) 3 (b) Give and explain CMOS input & output protection circuits.(10 marks) 4 (a) Implement 4×4 barrel shifter using transmission gate. Explain various operation using the same.(10 marks) 4 (b) Explain programming techniques used for EEPROM.(10 marks) 5 (a) What are the drawback dynamic CMOS logic. Show the modification in dynamic CMOS logic to over come it's drawback.(10 marks) 5 (b) Explain operation regions of CMOS inverter with equations.(10 marks)


Write short notes on.

6 (a) Interconnect scaling(7 marks) 6 (b) Cross talk.(7 marks) 6 (c) Array multiplier.(7 marks)

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