Question Paper: CMOS VLSI Design : Question Paper May 2013 - Electronics Engineering (Semester 8) | Mumbai University (MU)
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CMOS VLSI Design - May 2013

Electronics Engineering (Semester 8)

TOTAL MARKS: 100
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any four from the remaining questions.
(3) Assume data wherever required.
(4) Figures to the right indicate full marks.
1 (a) Analog circuit design is difficult as compared to digital circuit design. Justify.(5 marks) 1 (b) Explain electro migration in interconnect.(5 marks) 1 (c) Draw and explain trench capacitor and stacked capacitor structure of DRAM cell.(5 marks) 1 (d) Write a verilog code for 8-bit counter.(5 marks) 2 (a) Draw the circuit using propagate and generate term for 4-bit CLA network, in each of the following:-
(i) nFET logic
(ii) Pseudo nMOS logic.
(10 marks)
2 (b) Give and explain the capacitance associated with an interconnect and explain how propagation of signal depends upon the distributed RC effect.(10 marks) 3 (a) The storage capacitor in a DRAM has a value of Cs= 55F. The circuitry restricts the capacitor voltage to a value of Vmax=3.5 V; when the access transistor is off, the leakage current of the cell is estimated to be 75 nA.
1. How many electrons can be stored on CS?
2. How many fundamental charge unit q leave the cell in 1 second due to leakage current?
(10 marks)
3 (b) Give various important parameter affecting switching performance of CMOS inverter. Suggest method to improve it.(10 marks) 4 (a) Give and explain maximum and minimum frequency calculation of clock signal which determine the data transfer rate through cascade system.(10 marks) 4 (b) Implement following functions using AND-OR PLA:-
(i) X = ac + b
(ii) Y = abc + abc
(iii) Z = ab + ab.
(10 marks)
5 (a) Give and explain interconnect scaling with its width, length, thickness and capacitances. (10 marks) 5 (b) Give and explain single phase clock system and explain its drawbacks.(10 marks) 6 (a) Draw and explain CMOS two stage op-amp. Give gain boosting technique.(10 marks) 6 (b) Draw and explain Schmitt-trigger circuit as a input protection for CMOS. Also explain bi-directional i/o circuits.(10 marks)


Write short notes on any three:-

7 (a) Frequency compensation schemes for CMOS amplifier.(7 marks) 7 (b) Manchester carry circuits and MODL circuits.(7 marks) 7 (c) Pipelined system.(7 marks) 7 (d) EEPROM programming technique.(7 marks)

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