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Design a VHDL Code for Half Adder.
written 6.3 years ago by | modified 2.2 years ago by |
Subject: Digital System Design
Topic: Introduction to VHDL
Difficulty: High
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written 6.3 years ago by | modified 2.2 years ago by |
Subject: Digital System Design
Topic: Introduction to VHDL
Difficulty: High
written 6.1 years ago by |
Design a VHDL Code for Half Adder:
ENTITY half_adder IS --- Half Adder
PORT(a,b:IN BIT; s,c :OUT BIT);
END half_adder;
ARCHITECTURE half_adder_beh OF half_adder IS
BEGIN
s <= a XOR b; -- Implements Sum for Half Adder
c <= a AND b; -- Implements Carry for Half Adder
END half_adder_beh;