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Design a VHDL Code for Half Subtractor.
written 6.3 years ago by | modified 2.2 years ago by |
Subject: Digital System Design
Topic: Introduction to VHDL
Difficulty: High
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written 6.3 years ago by | modified 2.2 years ago by |
Subject: Digital System Design
Topic: Introduction to VHDL
Difficulty: High
written 6.1 years ago by |
VHDL Code for Half Subtractor:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hs1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
diff : out STD_LOGIC;
borrow : out STD_LOGIC);
end hs1;
architecture Behavioral of hs1 is
begin
diff<=a xor b;
borrow<=(not a) and b;
end Behavioral;