0
1.3kviews
Design a VHDL Code for Full Subtractor.
written 6.2 years ago by | modified 2.2 years ago by |
Subject: Digital System Design
Topic: Introduction to VHDL
Difficulty: High
ADD COMMENT
EDIT
1 Answer
written 6.2 years ago by | modified 2.2 years ago by |
Subject: Digital System Design
Topic: Introduction to VHDL
Difficulty: High
written 6.0 years ago by |
VHDL Code for Full Subtractor:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fs1 is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
bin : in STD_LOGIC;
d : out STD_LOGIC;
bout : out STD_LOGIC);
end fs1;
architecture Behavioral of fs1 is
begin
d<=x xor y xor bin;
bout<=((not x)and y)or((not x)and bin)or(y and bin);
end Behavioral;