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Design a VHDL Code for 4:2 Encoders.
written 6.3 years ago by | modified 2.3 years ago by |
Subject: Digital System Design
Topic: Introduction to VHDL
Difficulty: High
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written 6.3 years ago by | modified 2.3 years ago by |
Subject: Digital System Design
Topic: Introduction to VHDL
Difficulty: High
written 6.1 years ago by |
VHDL Code for 4 to 2 encoder using case statement:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity encoder is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : out STD_LOGIC_VECTOR(1 downto 0)
);
end encoder;
architecture bhv of encoder is
begin
process(a)
begin
case a is
when "1000" => b <= "00"; when "0100" => b <= "01"; when "0010" => b <= "10"; when "0001" => b <= "11"; when others => b <= "ZZ";
end case; end process;
end bhv;