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Explain (a) Slow rate (b) CMRR (c) input range Limitations (d) Power Supply Rejection Ratio
written 6.1 years ago by gravatar for hetalgosavi hetalgosavi • 1.6k modified 4.0 years ago by gravatar for prashantsaini prashantsaini • 0
cmos vlsi design
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written 6.1 years ago by gravatar for hetalgosavi hetalgosavi • 1.6k modified 6.1 years ago by gravatar for sanketshingote sanketshingote • 100

(a) Slew Rate:
i) Slew rate can be defined as maximum possible rate of change of op-amp output voltage.
$\hspace{2cm}SR=\frac{dV_0}{dt}|_{max}\,\,\,(V/\mu sec) $
$\hspace{8cm}$, ideally SR should be infinity.

ii) The slew rate imposes high frequency limitations on the device.
iii) At some critical frequency, an output swing equal to the …

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