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Explain Gain & phase margin condition while designing operational amplfiers

Subject: CMOS VLSI Design

Topic: MOS Operational Amplifiers

Difficulty: Medium

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Gain and Phase conditions while designing op-amp.

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$A_{CL}=\frac{A_{(S)}}{1+A_{(S)}\beta_{(S)}} ,\hspace{2cm}$ loop gain=$-A_{(S)}\beta_{(S)}$

Suppose above system has 2 poles $P_1$ and $P_2$, the Bode plot for mag & phase will have nature as follows,

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Assumptions:-
1) $P_1$ comes before $P_2$.

-> $P_2$ comes exactly at G B point. GBWpt is the point which gain=0.

2) $\phi_m$ (PM)

-> angle<-->GBW point (Here $\phi_m=45^0$) i.e minimum phase in design of op-amp should be $45^0$
-> Since, if unwanted pole comes, $\phi_m$ may become 0 before GBW pt and hence condition for -ve F/B will not be satisfied.

3) $G_m$

-> mag<-->$0^0$
-> For opamp, Gm-> -ve i.e phase should not get below $0^0$ before GBW point.

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