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Question Paper: Digital Logic Design & Analysis Question Paper - December 2016 - Computer Engineering (Semester 3) - Mumbai University (MU)

Digital Logic Design & Analysis - December 2016

MU Computer Engineering (Semester 3)

Total marks: --
Total time: --
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary
1(a) Convert decimal number 151.33 into binary, base-4, octal, hexadecimal system. 5 marks

1(b) A 7 bit even parity hamming code is received as 1000010. Correct it for any errors & extract 4 bit data. 5 marks

1(c) Express the equation in standard SOP from: F (A, B, C) = &squcap;M (0,2,5,7). 5 marks

1(d) Compare TTL & CMOS with respect to speed, power dissipation, fan-in & fan-out & also define these ters. 5 marks

1(e) Draw JK flip-flop using SR flip-flop & additional gates. Explain briefly the race around condition in JK flip-flop. 5 marks

2(a) Simplify the following equation using K-map to obtain minimum SOP equation & realize the minimum equation using two level NAND gates only. F (A, B, C, D)=⊓M(1, 3, 4, 6, 9, 11, 12, 14) 5 marks

2(b) What is Multiplexer? Implement the following function using 4:1 multiplexer and few gates. F(A, B, C, D) ∑m (0, 1, 2, 3, 6, 7, 9, 10, 13, 15) 5 marks

3(a) Reduce using Quine McClusky method & realize the equation using only NAND gates. F (P, Q, R, S) ∑m(0, 1, 2, 8, 10, 11, 14, 15) 5 marks

3(b) Prove using boolean algebra: "NAND gate is universal gate". 5 marks

4(a) Develop the truth tale for 2-bit binary multiplier & design it using a suitable decoder &additional gates. 5 marks

4(b) Design MOD-7 synchronous up-counter.Show all the design steps. 5 marks

5(a) Deveop the truth table of 3 bit binary to gray code converter and design it by using 3:8 decoder with active low outputs & additional gates. 5 marks

5(b) Draw a circuit diagram for MOD-10 asynchronous binary up counter using master-slave JK flip-flops. Show the output of each of the flip-flop with respect to the clock applied, write the state transition table and expalin the operation in brief. 5 marks

6(a) What is shift register? Draw a 4-bit universal shift register & explain PISO & SIPO operations. 5 marks

6(b) Draw & explain the working of 4-bit twisted ring counter with timing diagram. 5 marks

question paper mu • 52 views
written 13 days ago by gravatar for swatkat1127 swatkat1127 ♦♦ 0
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