Question Paper: Analog & Digital Circuits Question Paper - December 2016 - Information Technology (Semester 3) - Mumbai University (MU)
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Analog & Digital Circuits - December 2016

MU Information Technology (Semester 3)

Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

Solve any five Q1 (a,b,c,d,e,f)

1(a) What are the avrious regions that a transistor can operate? In which region can a transistor be operated if it is used as a switch? 5 marks

1(b) Give some applications of OpAmp and explain the block digram of Op Amp. 5 marks

1(c) Explain the working of LCD. 5 marks

1(d) Minimize the following boolean expression wsing K-map F(A,
B. C
D) = ∑m(0,
3,
7,
11,
11) +d(1,
2,
5)
5 marks

1(e) Draw the truth table and excitation table for S-Rflip flop. 5 marks

1(f) Convert (101101.1101) 2 to decimal,
octal and hexa decimal.
5 marks

2(a) What is the need for biasing? Explain voltage divider bias and locate the Q points 5 marks

2(b) Draw the truth table for all adder and realize using 3:8 decoder 5 marks

3(a) Explain the working of Monostable Multivibrator using IC555. Draw the waveforms and give its applications. 5 marks

3(b) Design and implement one digit BCD adder using IC-7483. 5 marks

4(a) Design and implement binary to gray code converter. 5 marks

4(b) Realize the following expression using only one 8:1 MUX and few logic gates F( A,
B,
C,
D) = ∑m(0,
3,
6,
6,
8,
11,
13,
15)
5 marks

4(c) Explain the practical differentiator circuit using op-Amp. 5 marks

5(a) Explain differential amplifier and elaborate on any one method to improve the CMRR. 5 marks

5(b) Design a half adder usign VHDL 5 marks

5(c) Design mod-3 up counter using JK Flip Flop 5 marks

write a short note any four Q6.(a,b,c,d,e)

6(a) Bidirectional shift register 5 marks

6(b) Full subtractor 5 marks

6(c) Basics Logic Gates 5 marks

6(d) BCD and Excess-3 code 5 marks

6(e) JFET 5 marks

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