Question Paper: Basic VLSI Design Question Paper - May 2015 - Electronics Engineering (Semester 6) - Mumbai University (MU)

Basic VLSI Design - May 2015

MU Electronics Engineering (Semester 6)

Total marks: --
Total time: --
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

Solve any four of the following:

1 (a) Explain the effect on drain current due to channel length modulation and velocity saturation. 5 marks

1 (b) Implementation using CMOS inverters. <mi>F</mi><mo>=</mo><mover><mrow><mi>A</mi><mo>⋅</mo><mi>B</mi></mrow><mo accent="false">¯</mo></mover><mo>=</mo><mi>C</mi></math>" role="presentation" style="font-size: 125%; text-align: center; position: relative;">F=¯¯¯¯¯¯¯¯¯¯¯¯AB=C<math xmlns="" display="block"><mi>F</mi><mo>=</mo><mover><mrow><mi>A</mi><mo>⋅</mo><mi>B</mi></mrow><mo accent="false">¯</mo></mover><mo>=</mo><mi>C</mi></math><script type="math/tex; mode=display" id="MathJax-Element-1"> F=\overline{A\cdot B}=C </script> 5 marks

1 (c) Draw voltage transfer characteristics for CMOS inverter and explain all regoins. 5 marks

1 (d) Give the read and write stability criteria for 6T RAM if the pull up transistors and replaced by resistors. 5 marks

1 (e) Explain low power design considerations. 5 marks

2 (a) Compare pass transistor logic, NMOS logic and CMOS logic. 5 marks

2 (b) For equal rise and tall delay five assume μn=2 μp draw an inverter equivalent circuit of 3 i/p NAND and 2 i/p XOR. 5 marks

3 (a) Compare constant voltage and constant field scaling with their merits and demerits. 5 marks

3 (b) Write short note on clock generation, stabilization and distribution. 5 marks

4 (a) Explain concept of carry look ahead with equation and how does it achieve better speed compared to ripple carry Adder. 5 marks

4 (b) Consider a CMOS inverter with following parameters
Nmos V to, n=0.6 V μn Cox=60 μA/V2 and (W/L)n=8
p mos V to, p=-0.7 V μn Cox=25 μA/V2 and (W/L)p=12
Calculate the noise margin and switching threshold (VTh) of this circuit, VDD=3V.
5 marks

5 (a) Implementation 4:1 multiplexer using pass transistor logic. 5 marks

5 (b) Explain concept of charge sharing and charge leakage. 5 marks

Write a short notes on any three of the following:-

6 (a) Sense amplifier 5 marks

6 (b) Array multiplier ( 4 × 4) 5 marks

6 (c) CMOS Latch up and it's prevention. 5 marks

6 (d) Resistance and capacitance estimation. 5 marks

written 9 months ago by gravatar for aniketbab1 aniketbab10
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