Question Paper: Basic VLSI Design Question Paper - May 2016 - Electronics Engineering (Semester 6) - Mumbai University (MU)
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## Basic VLSI Design - May 2016

### MU Electronics Engineering (Semester 6)

Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary
1(a) Draw and explain AND gate using pass transistor logic 5 marks

1(b) Explain drawback of dynamic CMOS design 5 marks

1(c) Draw and explain machester carry circuit. 5 marks

1(d) What are various programming teshniques used for EEPROM in explain them in short. 5 marks

2(a) Draw 6T SRAM cell and explain it's read and write operation. 5 marks

2(b) Define scaling? Explain various types of scaling in detail. 5 marks

3(a) Explain latch up condition in CMOS detail. What are remedies to avoid latchup. 5 marks

3(b) Give and explain the drawback of ripple carry adder. Explain 4 bit CLA adder with it's carry equations, logical network using dynamic CMOS logic. 5 marks

4(a) Explain how ESD (electrostatic discharge) affect the MOSFET. Give and explain input protection circuits. 5 marks

4(b) Give and explain interconnect scaling with its width, length, thickness and capacitances. 5 marks

5(a) Explain various technique of clock generation. Discuss 'H' tree clock distribution. 5 marks

5(b) Consider a CMOS inverter circuit with following parameters.
VDD = 3.3v VTon = 0.6v VTop = -0.7v, μnCox = 60 μ A/v2, (WL)n=8(WL)n=8 \displaystyle \left ( \dfrac{W}{L} \right )_n=8
μpCox = 20 μA/V2, (WL)p=1.2.(WL)p=1.2. \displaystyle \left ( \dfrac{W}{L} \right )_p=1.2. Calculate the noise margin.
5 marks

6(a) Sense ampliter 5 marks

6(b) Barrel shifter 5 marks

6(c) Interconnect parameters. 5 marks