Question Paper: VLSI Design Question Paper - December 2014 - Electronics Engineering (Semester 7) - Mumbai University (MU)
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VLSI Design - December 2014

MU Electronics Engineering (Semester 7)

Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary
1 (a) Draw a energy band diagram of MOS capacitor under external bias. 5 marks

1 (b) Compare buried and butting contact. 5 marks

1 (c) Implement following function using CMOS. <mi>F</mi><mo>=</mo><mover><mrow><mi>a</mi><mo>.</mo><mi>b</mi><mo>+</mo><mi>c</mi><mo>.</mo><mi>d</mi><mo>+</mo><mi>e</mi></mrow><mo accent="false">¯</mo></mover></math>" role="presentation" style="font-size: 125%; text-align: center; position: relative;">F=¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯a.b+c.d+e<math xmlns="http://www.w3.org/1998/Math/MathML" display="block"><mi>F</mi><mo>=</mo><mover><mrow><mi>a</mi><mo>.</mo><mi>b</mi><mo>+</mo><mi>c</mi><mo>.</mo><mi>d</mi><mo>+</mo><mi>e</mi></mrow><mo accent="false">¯</mo></mover></math><script type="math/tex; mode=display" id="MathJax-Element-1"> F=\overline{a.b+c.d+e} </script> 5 marks

1 (d) Draw the stick diagram for CMOS NOR gate. 5 marks

2 (a) Explain the various parameter affecting the threshold voltage of MOSFET. Explain the effect of ion implementation on threshold voltage of MOSFET. 5 marks

2 (b) Explain the complete fabrication process steps for CMOS Inverter using n-well process with the help of cross sectional diagram with all masking steps. 5 marks

3 (a) A CMOS symmetric inverter has following parameter
VDD=-3.3V, Vm=0.6V, Vtp=-0.7v.
kn=200 ?A/V2 kp=80 ?A/V2
Calculate noise margin of the circuit.
5 marks

3 (b) Define scaling-Discuss the advantages and disadvantages of different types of scaling. 5 marks

4 (a) Draw circuit diagram, stick diagram and layout for two input NOR gate using CMOS design rules. 5 marks

4 (b) Explain the operation of CMOS inverter with clearly mentioning the five cases given below.
i) Vin<v<sub>tn
ii) Vin=VIL
iii) Vin=VIH
iv) Vin>VDD+Vtp
v) Vin=VTH (Inverter threshold).</v<sub>
5 marks

5 (a) Write a verilog code for 4 bit ripple counter using D-FF as a basic component. 5 marks

5 (b) Compare passive load, active load NMOS inverter circuit with advantages and disadvantages. 5 marks

6 (a) Implement following Boolean function using CMOS logic <mi>y</mi><mo>=</mo><mover><mrow><mi>x</mi><mo>.</mo><mi>y</mi><mo>.</mo><mi>z</mi><mo>+</mo><mi>x</mi><mo>.</mo><mi>w</mi><mo>.</mo><mi>y</mi></mrow><mo accent="false">¯</mo></mover></math>" role="presentation" style="font-size: 125%; text-align: center; position: relative;">y=¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯x.y.z+x.w.y<math xmlns="http://www.w3.org/1998/Math/MathML" display="block"><mi>y</mi><mo>=</mo><mover><mrow><mi>x</mi><mo>.</mo><mi>y</mi><mo>.</mo><mi>z</mi><mo>+</mo><mi>x</mi><mo>.</mo><mi>w</mi><mo>.</mo><mi>y</mi></mrow><mo accent="false">¯</mo></mover></math><script type="math/tex; mode=display" id="MathJax-Element-2"> y=\overline{ x.y.z+x.w.y } </script> Draw stick diagram and layout of the circuit. 5 marks

6 (b) What is latch up in CMOS inverter and how to avoid it. 5 marks

Write short notes on any three:

7 (a) Hot electron effect. 5 marks

7 (b) Y-chart for design flow. 5 marks

7 (c) Design rules and their necessity. 5 marks

7 (d) Oxidation. 5 marks

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