Digital Electronics & Logic Design - December 2013

SPPU Information Technology (Semester 3)

Total marks: --
Total time: -- INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

Solve any one question from Q1 and Q2

1 (b) Compare totem pole and open collector output configurations in TTL. 6 marks

2 (a) Draw and explain 2 inputs TTL NAND gate with Totem Pole Output. 6 marks

2 (b) Design Full adder using suitable Decoder. 6 marks

Solve any one question from Q3 and Q4

3 (b) Explain with a neat diagram working of 3 bit bidirectional shift register. 6 marks

4 (a) Explain the difference between Combinational and Sequential Circuit. Design S-R Flip-Flop using J-K Flip-Flop. 6 marks

4 (b) Design a sequence detector to detect the sequence ------- 110 ------- using J-K Flip-Flop. 6 marks

Solve any one question from Q5 and Q6

5 (b) Design a 4 bit BCD to Excess-3 code converter using PLA. 6 marks

6 (a) Explain difference between FPGA & CPLD. 6 marks

6 (b) Design the following function using PLA.
F₁=∑m(1, 2, 4, 6)   F₂=∑m(0, 1, 6, 7)   F₃=∑m(2, 6) 6 marks

Solve any one question from Q7 and Q8

7 (b) Explain Process statement in behaviour model of VHDL with respect to syntax, sensitivity list, declarative part and statement part. 6 marks

8 (a) Explain the difference between VHDL Modelling styles-Data Flow, Behavioural and Structural 6 marks

8 (b) Explain data objects in VHDL - signals, variables and Constants. 6 marks