Question Paper: Digital Electronics & Logic Design Question Paper - June 2015 - Information Technology (Semester 3) - Savitribai Phule Pune University (SPPU)
0

## Digital Electronics & Logic Design - June 2015

### SPPU Information Technology (Semester 3)

Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

### Answer any one question from Q1 and Q2

1 (a) Represent the following decimal numbers in single precision floating point format:
i) 255.5
ii) 110.65
6 marks

1 (b) What do you mean by open collector output ? Explain with suitable circuit diagram. What is the advantage of this output? 6 marks

2 (a) Perform 2's complement arithmetic of:
i) (7)10-(11)10
ii) (-7)10-(11)10
iii) (-7)10+(11)10
6 marks

2 (b) Draw suitable circuit diagram and explain the drawback of WIRED_OR TTL GATE? 6 marks

### Answer any one question from Q3 and Q4

3 (a) What is race around condition? Explain with the help of timing diagram. How is it removed in basic flip-flop circuit? 6 marks

3 (b) Design a sequence generator using shift register and decoder circuit to generate the sequence ......1101011...... . 6 marks

4 (a) How will you convert the basic SR-flip-flop (SR-FF) into JK- Flip-flop? 6 marks

4 (b) Design a MOD-11 counter using IC7490. Show states with the help of timing diagram. 6 marks

### Answer any one question from Q5 and Q6

5 (a) Draw the basic structure FPGA. Explain its feature in brief. 6 marks

5 (b) Implement the following function using programmable logic Device:
i) F1 = ∑(0, 3, 4, 7)
F2= ∑m(1, 2, 5, 7)
6 marks

6 (a) Draw the basic structure of CPLD. Explain its features in Brief. 6 marks

6 (b) Design a BCD to Excess-3 code converter using suitable programmable logic device. 6 marks

### Answer any one question from Q7 and Q8

7 (a) State and explain different data types supported by VHDL. 6 marks

7 (b) Write features of VHDL. Explain entity architecture declaration for 2 bit NOR and AND gate. 6 marks

8 (a) State and discuss different types of operators used in VHDL. Give precedence of these operators. 6 marks

8 (b) Describe different modelling styles of VHDL with suitable example. 6 marks