Question Paper: VLSI Design Question Paper - May 2016 - Electronics and Telecom Engineering (Semester 6) - Mumbai University (MU)
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VLSI Design - May 2016

MU Electronics and Telecom Engineering (Semester 6)

Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

Attempt any FOUR from the following

1(a) For NMOS resistive load inverter with RL=50K find VIL and VOL if VDD=5V, VTO=1V, Kn=100 μA/V2, neglect body bias effect and channel length modulation. 5 marks

1(b) With help of appropriate circuit diagram and waveforms, explain charge sharing problem of dynamic logic. How to overcome the same. 5 marks

1(c) Explain the significance of Level-1 MOSFET model parameters. 5 marks

1(d) Implement 4:1 MUX using Transmission gate technology. 5 marks

1(e) Explain advantages and disadvantages of Pass Transistor logic in VLSI Design. 5 marks

2(a) Explain working of CMOS Inverter with help of Voltage Transfer Characteristics and derive expression for VIL and VIH. 5 marks

2(b) Implement 1-bit full adder circuit using standard CMOS logic, dynamic logic and pseudo NMOS logic. 5 marks

3(a) Draw six transistor SRAM cell and explain its read 0, read 1, write 0 and write 1 operation with the help of appropriate waveforms. 5 marks

3(b) What is Carry Look Ahead (CLA)adder. Write equations for carry propagate and implement the same using domino logic. 5 marks

4(a) For 2 input CMOS NAND gate find VOL, VOH, VIH, and VIL. Assume that both the inputs are switching simultaneously. Consider NMOS and PMOS with following parameters. VDD=5V, VTOn=1V, Kn=100μA/V2, VTOp=-1V, Kp=25μA/V2. 5 marks

4(b) Give NMOS fabrication process flow with help of neat sketches of appropriate masks and cross section at each process steps. 5 marks

5(a) Implement 4×4 NAND based ROM array to store '1001', '0101', '1010' and '1100' in the memory. 5 marks

5(b) Explain the effect of Interconnect scaling on various performance parameters of VLSI circuits. 5 marks

5(c) Draw layout of 3 transistor (3-T) DRAM cell using lambda rules. 5 marks

Write short notes on any FOUR

6(a) Power Distribution schemes 5 marks

6(b) Array Multiplier 5 marks

6(c) Interconnect Delay Model 5 marks

6(d) NAND Flash Memory 5 marks

6(e) Column Decoders 5 marks

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