Question Paper: VLSI Design Question Paper - December 2015 - Electronics and Telecom Engineering (Semester 6) - Mumbai University (MU)

VLSI Design - December 2015

MU Electronics and Telecom Engineering (Semester 6)

Total marks: --
Total time: --
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

Solve any five from the following:

1 (a) Explain Level 1 and Level 2 MOSFET model used in circuit simulator. 5 marks

1 (b) In 2 input CMOS NAND gate all PMOS transistor have (WL)=20(WL)=20\left ( \dfrac {W}{L} \right )=20 and all NMOS transistor have (WL)n=10(WL)n=10 \left ( \dfrac {W}{L} \right )_n =10 . Draw its equivalent CMOS inverter and find size of PMOS and NMOS transistor in the equivalent inverter circuit. 5 marks

1 (c) What are advantages & disadvantages of dynamic logic circuit. 5 marks

1 (d) Why sense amplifier is used in memory circuit. Explain its working. 5 marks

1 (e) How low power circuit is designed through voltage scaling. 5 marks

1 (f) Explain hot carrier in short channel MOSFET. 5 marks

2 (a) Compare resistive load inverter, saturated load inverter and CMOS inverter on the basis of Noise margins, power dissipation, area and delay. 5 marks

2 (b) Draw 2 input CMOS NOR gate and using equivalent inverter approach and derive expression for Vm' VIH' VOL and VOH. 5 marks

3 (a) Design clocked D-FF and implement using standard CMOS logic style. 5 marks

3 (b) Draw layout of six transistor CMOS SRAM using lambda rule. 5 marks

4 (a) Explain 4-bit x 4-bit array multiplier with the help of necessary hardware for the generation and addition of partial product. 5 marks

4 (b) Why ESD protection is required for CMOS chips. Explain various techniques of ESD protection. 5 marks

5 (a) Implement y=A (D+E)+BC using
i) Static CMOS style
ii) Pseudo NMOS logic style
iii) Dynamic logic style
Transmission Gate logic
5 marks

5 (b) What are different types of MOSFET scaling? Explain advantages and disadvantages of each using appropriate equations. 5 marks

Write short notes on any four:

6 (a) (i) 3T-DRAM cell 5 marks

6 (a) (ii) Clock distribution in VLSI system 5 marks

6 (a) (iii) Barrel shifter. 5 marks

6 (a) (iv) C2MOS logic style 5 marks

6 (a) (v) 1-bit shift register. 5 marks

written 9 months ago by gravatar for aniketbab1 aniketbab10
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