Question Paper: VLSI Design Question Paper - May 2017 - Electronics and Telecom Engineering (Semester 6) - Mumbai University (MU)
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## VLSI Design - May 2017

### MU Electronics and Telecom Engineering (Semester 6)

Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

### Solve any four question from Q.1(a, b, c,d, e)

1(a) Compare NMOS & CMOS technology in VLSI design. 5 marks

1(b) Implement the following function using Dynamic CMOS logic <mi>Y</mi><mo>=</mo><mover><mrow><mi>A</mi><mo stretchy="false">(</mo><mi>B</mi><mo>+</mo><mi>C</mi><mo stretchy="false">)</mo></mrow><mo accent="false">¯</mo></mover>[/itex]" role="presentation" style="font-size: 125%; text-align: center; position: relative;">Y=¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯A(B+C)<math xmlns="http://www.w3.org/1998/Math/MathML" display="block"><mi>Y</mi><mo>=</mo><mover><mrow><mi>A</mi><mo stretchy="false">(</mo><mi>B</mi><mo>+</mo><mi>C</mi><mo stretchy="false">)</mo></mrow><mo accent="false">¯</mo></mover>[/itex]<script type="math/tex; mode=display" id="MathJax-Element-1"> Y=\overline{A(B+C)}</script> 5 marks

1(c) Compare Ripple carry adder with CLA. 5 marks

1(d) Explain working principle of flash memory. 5 marks

1(e) Explain importance of low power design. 5 marks

2(a) Compare the full scalling & constant voltage scalling models of MOSFET Demonstrate the effect of scalling on the area, delay, power consumption and current density of the device. 5 marks

2(b) Expalin transfer characteristic of NMOS inverter showing different regions, what is the effect of variation in W/L ratio? 5 marks

3(a) Draw 1T DRAM cell and explain it's write read hold & refresh operation. 5 marks

3(b) Explain scheme for multiplication on 101*010. 5 marks

4(a) Explain various techniques of clock generation & clock distribution . 5 marks

4(b) Consider a CMOS inverter circuit with following parameters
VDD=3.3v.
V To.n = 0.6v.
V To.p = 0.7v
Kn = 200μ A/v2
Kp= 80 μ A/v2
Calculate noise Margins of the circuit Consider KR = 2.5 & V To.n ≠V ro.p
5 marks

5(a) Draw JK Flip Flop using CMOS and explain the working. 5 marks

5(b) Draw CLA ( carry look head adder) carry chain using dynamic CMOS logic. 5 marks

### Write short note any three question from Q.6(a,b,c,d)

6(a) Latch up in CMOS 5 marks

6(b) Sense Amplifier 5 marks

6(c) Interconnect scaling. 5 marks

6(d) 4*4 Barel shifter. 5 marks