Question Paper: Analog Electronics - 1 Question Paper - December 2016 - Electronics and Telecom Engineering (Semester 3) - Mumbai University (MU)

Analog Electronics - 1 - December 2016

MU Electronics and Telecom Engineering (Semester 3)

Total marks: --
Total time: --
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

Solve any question 4 Q1(a,b,c,d,e,f)

1(a) For the circuit given below, the transistor parameter are Vp=-3.5ν,
IDSS=18mA and λ=0. Calculate VGS and VDS.
5 marks

1(b) The small- signal parameters of the NMOS transistor in the source follower circuit shown in fig. below are gm=5mA/V and ro= 100kΩ Determine the voltage gain and output resistance.
5 marks

1(c) Design a diode clamper to generate a steady- State output voltage Vo from the input voltage Vi in fig. Shown below if diode is Ideal.
5 marks

1(d) For the circuit shown, determine RE such that the emitter current is limited to IE=1mA, Also find IB (Given α=0.9920) 5 marks

1(e) Describe the channel length modulation effect and define the parametersλ. 5 marks

1(f) Draw a neat circuit diagram of emitter follwer configuration and its hybrid-πmodel. 5 marks

2(a) Determine the following for the network given below
i) Q-point
ii) Av,
5 marks

2(b) Explain the working of Wein Bridge oscillator. Derive the expression for frequency of oscillation and condition of oscillation. 5 marks

3(a) Draw output waveform for clipper and clamper circuits shown.
5 marks

3(b) Explain construction and characteristics of n-channel Depletion MOSFET. Draw transfer characteristics and drain characteristics. 5 marks

4(a) Find ICQ and VCEQ for the circuit shown in figure if β=100
5 marks

4(b) For the circuit in fig. Let β=100,
VBF(on)=0.7V. Determine
i) Small signal voltage gain
ii) Input resistance seen by the signal source
iii) Output resistance
5 marks

5(a) For the amplifier circuit shown below
i) Determine the values of Kp such that VSDQ=6V
ii) Determine the resulting value of IDQ and small voltage gain.
5 marks

5(b) Draw circuit diagram of common source amplifier with voltage divider bias with unbypassed source resistance 'Rs' using n-channel EMOSFET. Derive expression for voltage gain, input resistance and output resistance. 5 marks

Write short note on any four Q6(i,ii,iii,iv,v)

6(i) Energy band diagram of MOS capacitor 5 marks

6(ii) Construction and operation of Schottkydiode 5 marks

6(iii) Crystal Oscillator 5 marks

6(iv) Hybrid parameters 5 marks

6(v) Stability factor of biasing circuit. 5 marks

written 5 months ago by gravatar for aniketbab1 aniketbab10
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