The Cortex-M3 supports a number of exceptions, including a fixed numberof system exceptions and a number of interrupts, commonly called IRQ.

The number of interrupt inputs on a Cortex-M3 microcontroller dependson the individual design.

Interrupts generated by peripherals are connected to the interrupt inputsignals (16 or 32 in number).

There is also a non maskable interrupt (NMI) input signal.

The NMI could be connected to a watchdog timer or a voltage-monitoringblock that warns the processor when the voltage drops below a certain level.

Interrupt Vector Table.

When an exception event takes place on the Cortex-M3 and is accepted bythe processor core, the corresponding exception handler is executed.

To determine the starting address of the exception handler, a vector tablemechanism is used.

The vector table is an array of word data inside the system memory, eachrepresenting the starting address of one exception type.

The vector table is re-locatable, and the relocation is controlled by arelocation register in the NVIC.

After reset, this relocation control register is reset to 0; therefore, thevector table is located in address 0x0.

The LSB of each exception vector indicates whether the exception is to beexecuted in the Thumb state. Because the Cortex-M3 can support onlyThumb instructions, the LSB of all the exception vectors should be set to 1.