Step A –

This process begins with the preparation of the GaAs wafer. To prepare the substrate, the GaAs wafer is slightly etched to remove about 100 nm to remove surface oxide, contamination and damage from packaging and handling. A silicon nitride insulating layer is then deposited by reactive sputtering to a thickness of 100 nm. This capping layer protects the GaAs surface during the entire processing operation and helps to prevent loss of As from the surface by decomposition of the GaAs during high temperature processing.

Step B –

Step B (mask #1) in the fabrication is the formation of the channel regions between the source and drain regions using a silicon ion implantation process. Since the GaAs substrate is semi-insulating, implantation of silicon ions is used to form a lightly doped but conducting, n-type region.. Positive resist is used to define the channel location and implantation is done through the silicon nitride cap layer. After implantation, the resist is removed for subsequent alignment of masks for the source and drain and gate regions. The resist is then stripped off the wafer leaving the nitride intact.

Step C –

Formation of the source and drain regions for the MESFET is done in the next masking step (mask #2) in a similar fashion. Positive resist is again used to define the area of the implant. The resist is then removed (stripped) after the implant. Since implantation produces severe damage to the semiconductor lattice, a thermal annealing step is needed after the implant to repair the damage and to activate the implanted species. This completes the formation of the active regions of the device.

Step D –

Next, to make electrical contacts to the device's source and drain regions, resist is applied and patterned (mask # 3) and openings in the silicon nitride are etched down to the semiconductor surface over the source and drain regions. After patterning, the resist is treated in chlorobenzene to swell its top surface and produce an overhanging ledge at the top of the resist in the windows. The underlying silicon nitride is etched away in the windows to expose the underlying GaAs surface.

Step E –

The contact metal Au/Ge/Ni is then deposited patterned and the excess metal removed (lifted off) by dissolving the resist in a solvent.

Step F –

The same lithography process and liftoff technique is also used to pattern the aluminum Schottky metal (mask #4) to form the gate electrode for the MESFET.

Step G –

The MESFET's fabrication is now complete and the device is ready for testing and electrical characterization. The fabrication process outlined above is a basic one with a minimum of mask levels and processing.