Question Paper: Logic Design Question Paper - Dec 17 - Information Technology (Semester 3) - Mumbai University (MU)

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## Logic Design - Dec 17

### Information Technology (Semester 3)

Total marks: 80

Total time: 3 Hours
INSTRUCTIONS

(1) Question 1 is compulsory.

(2) Attempt any **three** from the remaining questions.

(3) Draw neat diagrams wherever necessary.

Q1) Solve any four

**1(a)**Prove that NOR gate is a universal gate.

**1(b)**Convert following decimal number to Binary, Octal, Hexadecimal and Gray code $(2538)_{10}$

**1(c)**Derive relation between $\alpha$ and $\beta$

**1(d)**Design full adder using half adder and additional gates.

**1(e)**Convert D flip flop to T flip flop.

**2(a)**Explain Voltage Divider Biasing Circuit with its stability factor.

**2(b)**Using Quine MC Cluskey Method determine Minimal SOP form for

$$ F(A, B, C, D) = \sum m (0,1,3,7,8,9,11,15) $$

**3(a)**Implement following using only one 8:1 multiplexer and few gates.

$$ F(A,B,C,D) = \sum m (0,1,3,4,5,7,9,10,12,15)$$

**3(b)**With neat logic diagram explain operation of 4-bit Bidirectional Shift Register.

**4(a)**Design a Mod 12 asynchronous counter using J-K Flipflop.

**4(b)**Minimize the following four variable logic function using K-map.

(i) $f(A, B, C, D) = \sum m (0,1,3,4,7,9,11,13,15)$ 1462

(ii) $f(A, B, C, D) = \pi M (0,2,5,6,10,12,13.14)$

**5(a)**Simplify following equation using Boolean Algebra and Design using basic gates.

i) $(A + B) (A+C)$

ii) $(A + C) (AD + A \overline D) + AC + C$

**5(b)**Explain VHDL program format and write VHDL program for NAND gate.

Q6) Solve any four

**6(a)**3-bit binary to Gray code conversion.

**6(b)**Working of Master slave J-K flip flop.

**6(c)**Explain working current mirror circuit.

**6(d)**Write VHDL program for Half Subractor circuit.

**6(e)**Explain working of 3:8 Decoder.