Electronics Engineering (Semester 7)
Total marks: 80
Total time: 3 Hours
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.
Q1) Solve any four of the following (any four).
Explain various charges in the gate oxide after fabrication of MOSFET.
What is Trench Isolation? Explain its use in VLSI technology.
Classify crystal structure with respect to resistivity and periodicity of atoms.
Enlist the steps for obtaining Silicon from Sand.
Explain Molecular Beam Epitaxy.
Define Range , Projected Range and straggle with respect to ion Implantation. Also explain the damage produce due to light Ion and heavy Ion with neat diagram.
Describe APCVD process with neat diagram. Why wafers are lying horizontal in this process. Enlist drawbacks of this process.
List out common Unit processes in IC Fabrication. What is the Difference between N-Well and P-Well process? Draw final cross - sectional view of CMOS inverter fabrication using N – Well process with appropriate labels?
Draw layout of CMOS inverter along with its circuit diagram. Mention Clearly all dimensions as per lambda rules. Explain buried and butting contact.
Explain Steps of Lithography with suitable diagrams. Also classify Lithography techniques.
What is SOI technology? Enlist methods for fabrication of SOI. Explain any one of it.
Describe with the help of a neat diagram Hayness-Schokley experiment for measurement of Drift Mobility of n-type semiconductor.
Compare evaporation and sputtering methods for metal deposition. Which Methods are commonly used for deposition of Silicon, SiO 2 and metals?
Q6) Write short notes on any four of the following.
Parametric test and functionality test for IC testing
Electric package reliability.
Silicon Crystal defects
Multiagte device Structures
MESFET fabrication process