A universal shift register is a bidirectional register, whose input can either in serial form or in parallel form and whose output can also be either in serial form or in parallel form.

Following figure shows the logic diagram of the 74194 4-bit universal shift register. Note that the output of each flip flop is routed through AOI logic to the stage on its right and to the stage on its left. The mode control inputs S0, and S1, are used to enable the left to, right connections when it is desired to shift-right, and the right-to-left connections when it is desired to shift-left.

The truth table shows that no shifting occurs when S0 and S1 are either LOW or both HIGH. When So = S1=0, there is no change in the contents of the register, and when So = S1 = 1, the parallel input data A, B, C and D are loaded into the register on the rising edge of the clock pulse. The combination S0 = S1= 0, is said to inhibit the loading of serial or parallel data, since the register contents cannot change under that condition. The register has an asynchronous active-Low clear input, which can be used to reset all the flip flops irrespective of the clock and any serial or parallel inputs.