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Computer Organization And Architecture Question Paper - May 17 - Computer Engineering (Semester 4) - Mumbai University (MU)
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Computer Organization And Architecture - May 17

Computer Engineering (Semester 4)

Total marks: 80
Total time: 3 Hours

Instructions
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume Suitable data if required. (4) Draw neat diagrams wherever necessary.

Q1 Solve any four out of five

1.a. Explain virtual memory
(5 marks) 5798

1.b. What is IO buffering?
(5 marks) 12547

1.c. Write a short note on scanner.
(5 marks) 12548

1.d. What is segmentation.
(5 marks) 12549

1.e What is TLB?.
(5 marks) 12550

2.A.1 Draw the flow chart for restore division algorithm.
(4 marks) 12551

2.A.2 Divide using restore division method.
(6 marks) 00

2.B Describe Hard-wire control unit and specify its advantage
(10 marks) 5785

3.a Multiply (-5) and (2) using Booth's Algorithm.
(10 marks) 5773

3.b A block set associative cache consist of 64 blocks divided in 4 block sets. The main memory contains 4096 blocks, each 128 words of 16 bit length.

  1. How many bits are there in main memory address?

  2. How many bits are there in cache memory address (tags, set and word fields)?

(10 marks) 12552

4.a Differentiate between I, RISC and CISC processor.
(10 marks) 12553

4.b Explain Flynn's classification.
(10 marks) 5815

5.a Discuss the functions of 8089 I/O processor.
(10 marks) 5806

5.b Show IEEE 754 standards for Binary Floating Point Repersentation for 32 bit single format and 64 bit double format.
(10 marks) 5775

6.a Explain different pipelining hazards.
(10 marks) 12554

6.b Discuss the functions of DMA.
(10 marks) 5802

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