Draw JK Flip Flop using CMOS and explain the working.

24kviews

written 5.4 years ago by

hetalgosavi • 1.6k

• modified 5.1 years ago

Subject :- VLSI Design

Topic :- MOS Circuit Design Styles

Difficulty :- High

vlsi design

ADD COMMENT EDIT

1 Answer

4.4kviews

written 5.1 years ago by

hetalgosavi • 1.6k

The problem in clocked SR latch, in which when both inputs S and R are activated at the same time, not allowed condition comes, hence to overcome this, two feedback lines are added from the output to input as shown below, and resulting circuit is called as JK latch.

Consider …

Create a free account to keep reading this post.

and 4 others joined a min ago.

ADD COMMENT EDIT

Please log in to add an answer.