• The parasitic devices that are formed in CMOS inverter are - Parasitic Resistance (R), Parasitic Capacitance (C), Parasitic Diode (D), Parasitic BJT, Parasitic SCR

  

• $Q_1$ is the PNP transistor and $Q_2$ is the NPN transistor. This forms a regenerative forward bias Pair that represents SCR in forward blocking mode.

• $R_P$ is the P-well resistance and $R_S$ is the N-Si substrate resistance.

Working

• Since nMOS & pMOS transistor must be fabricated on the same chip side by side, COMS process is more complex as compared to standard nMOS only.
• In particular the COMS process must provide a N-substrate for the pMOS transistor and vice versa.
• This can be achieved by building either n-type well and p-type wafer or vice-versa.
• However, the close proximity of nMOS & pMOS transistor may result in to formation of 2 parasitic BJTs causing a latch-up problem.

Latch up Mechanism

• Due to increase in ambient temperature, incident radiation electromagnetic interference power supply transients a small leakage current is drawn by N-Si substrate from supply i.e. $I_S$
• $I_S$ causes drop across $R_S$.
• If drop is sufficient enough to forward bias Base-Emitter junction of Q1 then Q1 conducts.
• Due to this P-well draws a current through Q1 and therefore potential drops across $R_P$
• If drop is high enough to forward bias Base-Emitter junction of Q2, then Q2 conducts.
• Q2 conducts and then Q1 & Q2 self-sustained ON state and then SCR turns ON.
• If SCR is ON then there exists low resistance path VDD to ground.
• Therefore current increases abruptly to large value and thus the device melts
• This destructive phenomenon is called COMS latch up.

Prevention of CMOS latch up

• One method of preventing latch up is to decrease the parasitic transistor current gain. If the product of two current gains β1.β2 < 1, then forward bias is not self-sustaining and hence device cannot latch.
• The current gain of PNP transistor is determined by the process design and can be decreased by using buried layer of $N^+$ materials.
• The NPN transistor current gain can be reduced by increasing the space between the $N^+$ source, drain & well.
• This will increase the width of transistor base and hence current gain will decrease.
• Second method is to keep VDD and ground contacts as shown in figure. By defining multiple contacts we reduce the resistance offered by well as well as the substrate.
• By using dielectric isolation between pMOS & nMOS transistor leakage current can be decreased and hence latch up can be prevented.