Question: Explain the significance of TEST*, RESET, and MN/MX* signals in 8086 processor ( * indicate bar )

Mumbai University > Electronics and Telecommunication > Sem 4 > Microprocessor and peripherals

mumbai university mpa • 204 views
modified 12 weeks ago by gravatar for Ankit Pandey Ankit Pandey60 written 5 months ago by gravatar for kazi.tahoor kazi.tahoor0


It is an input pin and is only used by the wait instruction. The 8086 enter a wait state after execution of the wait instruction until a low is seen on the test pin. If the TEST pin is Low, execution continues otherwise the processor waits in an "idle" state. This input is synchronised internally during each clock cycle on the leading edge of CLK.

RESET : Reset causes the processor to immediately terminate its present activity. To be recognized, the signal must be active high for at least four clock cycles, except after power-on which requires a 50 Micro Sec. pulse. It causes the 8086 to initialize registers DS, SS, ES, IP and flags to all zeros. It also initializes CS to FFFF H. Upon removal of the RESET signal from the RESET pin, the 8086 will fetch its next instruction from the 20 bit physical address FFFF0H. The reset signal to 8086 can be generated by the 8284. (Clock generation chip). To guarantee reset from power-up, the reset input must remain below 1.5 volts for 50 Micro sec. after Vcc has reached the minimum supply voltage of 4.5V.


This pin indicates what mode the processor to operate in. In minimum mode, the 8086 itself generates all bus control signals. In maximum mode the three status signals are to be decoded to generate all the bus control signals.

MN/MX is an input pin used to select one of this mode. When MN/MX is high the 8086 operates in minimum mode .In this mode the 8086 is configured to support small single processor system using a few devices that the system bus .When MN/MX is low 8086 is configured to support multiprocessor system.

written 12 weeks ago by gravatar for Ankit Pandey Ankit Pandey60
Please log in to add an answer.