Mumbai University > Electronics and Telecommunication > Sem 4 > Microprocessor and peripherals
Need for DMA :
- In I/O data transfer ,data is transferred by using microprocessor . The microprocessor will read data from I/O device and then will write data to memory.In this case there are two operations for single data transfer.
- If the data is less ,then microprocessor will not waste its time ,transferring data from I/O to memory or back. But suppose data is large ,then the transfer rate from I/O to memory or back will slow down because of microprocessor intervention .
- In such cases to speed up the process of transferring the data we can think of Direct Memory Access (DMA)controller i.e direct transfer between memory and I/O but under supervision . The device which supervises data transfer is called as DMA Controller.
DMA transfer Modes :
Rotating Priority mode :
If the RP bit of mode set register is set then the 8257 operates in rotating priority mode . After each DMA cycle ,the priority of each channel changes.
Hence all the channels will get equal opportunity ,if they are enabled and their DMA requests exists. Initially CH- 0 gains highest priority while CH - 3 gains lowest priority .The channel which is just been serviced will get the lowest priority after the DMA cycle and other channels move to the next higher priority levels.
Fixed Priority Mode :
If the RP bit of mode set register is reset then 8257 operates in fixed priority mode. In fixed priority mode ,channel 0 has highest priority and channel 3 has lowest priority.
The priority is resolved during state 4 of each DMA cycle.
TC Stop Mode :
If the TC stop bit in mode set register is set ,then 8257 disables the channel whose TC is reached. Thus it stops further DMA operations on that channel.
If the TC stop bit is reset ,then the TC have no effect on channel,corresponding channel must be disabled by the microcomputer system through software.
The TC stop bit option should be common for all channels
Extended Write Mode :
If the EW bit of mode set register is set ,then 8257 generates advacned or extended write control signals i.e the write signal will go low one clock cycle earlier .
This mode is used to interface slower devices to the system. If the memory deivce or I/o device connected is slower ,then for synchronization READY signal is used.
In this method the write signal is delayed by adding wait states into a DMA cycle. This reduces the speed of transfer.
But in extended write mode ,the write signal is extended earlier without adding states i,e the set up time of write input signal of an I/o device or memory is increased in extended write mode without reducing the speed of transfer.
This signal allows more time to external logic for deciding if additional wait states are needed.
Autoload Mode :
If AL bit of mode set register is set,the 8257 operates in autoload mode. In this mode the data is transferred by channel 2 only i.e other channels are not used for data transfer.
It can be used for repeat block or block chaining operations.
Repeat Block Operation :
If the AL bit is set,the parameters (memory address and terminal count ) of CH - 2 are duplicated into CH -3 register.The EN3 and TC bits are irrelevant.
The new parameters are not written into the CH - 3 registers. THe CH -2 transfers forst DMA block between memory and I/ o device . After transferring first DMA block ,the 8257 executes an 'Update cycle' .During this cycle the contents of CH - 3 register are transferred to CH - 2 register and update flag is set in status register.
Thus the repeat block operation continues with the programming of only CH -2 . It can be used in CRT or LED refreshing.
Block Chaining Operation :
In this operation CH -2 transfers two or more different data blocks . CH - 3 must be loaded with diferent parameters after initializaton of CH - 2 registers. In this mode both the channels have to be enabled. The TC stop bit is irrelevant.
Initially CH- 2 and CH - 3 register are initialized with block 1 and block 2 parameters respectively . Then CH - 2 transfers data block.
During last DMA cycle it activates TC signal and sts the update flag.The 8257 executes update cycle and transfers contents of CH - 3 registers into CH-2 registers.
The update flag is cleared at the end of first DMA cycle of next data block. The microprocessor writes new parameter into CH -3 registers
The CH- 2 then transfers second byte of next data block . In this way CH -2 transfers two or more data blocks. The TC signal can be used to interrupt the microprocessor to load block parameters.