Ask
Login
1
4.7kviews
Explain in detail charge pump PLL
written 5.3 years ago by gravatar for hetalgosavi hetalgosavi • 1.6k modified 4.0 years ago by gravatar for prashantsaini prashantsaini • 0
cmos vlsi design
ADD COMMENT EDIT
1 Answer
0
455views
written 5.2 years ago by gravatar for hetalgosavi hetalgosavi • 1.6k
  • The charge pump circuit senses the transition at input and output, detects phase or frequency differences, and activates the charge pump accordingly.
  • When the input and output frequencies are sufficiently close, the PFD (Phase Frequency Detector) operates as the phase detector, performing phase lock operations.
  • The loop locks when the phase difference drops to zero and the charge pump remains relatively idle.
  • Ignoring the narrow reset pulse on $Q_A$ and $Q_B$ and assume that Φout - Φin drops to zero, the PFD simply produces $Q_A$ = $Q_B$ = 0
  • The charge pump thus remains idle and Cp sustains a constant control voltage.
  • The charge pump PLL responds to only excess phase of waveform.

  • The phase comparison is performed in every cycle, but the VCO phase and frequency cannot drift substantially.
ADD COMMENT EDIT
Please log in to add an answer.