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VLSI Design Question Paper - Dec 18 - Electronics And Telecomm (Semester 6) - Mumbai University (MU)
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VLSI Design - Dec 18
Electronics And Telecomm (Semester 6)
Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.
Q1) Attempt any four from the following
a)
Draw VTC curve of static CMOS inverter and show all critical volatges ($V_{IL},V_{IH}, V_{OL}, V_{OH}$ and $V_{INV} $) on the plot. Also show current drawn by CMOS inverter on VTC.
(5 marks)
00
b)
Explain any two short channel efects in MOS transistor.
(5 marks)
00
c)
What are advantages and disadvantages of dynamic CMOS logic circuit?
(5 marks)
00
d)
Implement 4:1 multiplexer using NMOS pass transistor logic.
(5 marks)
00
e)
Explain different CMOS clocking styles.
(5 marks)
00
Q2)
a)
Consider a CMOS inverter circuit with the follwong parameters:
(10 marks)
00
$V_{DD}$ = 3.3V $V_{t0.n}$ = 0.6V $V_{t0.p}$ = -0.9V
$K_n$ = 200 $\mu a/V^2$ $K_p$ = 80 $\mu a/V^2$
b)
Implement $Y=\frac{}{A(B+C)(D+E)}$ using
(10 marks)
00
i) static CMOS logic style
ii) Dynamic logic
iii) Depletion load logic
iv) Pseudo NMOS logic
Q3
a)
Explain in detail the fabrication sequence of NMOS transistor with cross sectional view of each step.
(10 marks)
00
b)
Draw schematic of six transistor SRAM cell. Describe various constraints that should be imposed on the devices to guruantee safe and read and write operation. Also discuss relative sizing of the transistors in the cells.
(10 marks)
00
Q4
a)
Define scaling. Explain different types of scaling.
(10 marks)
00
b)
Construct a full adder mirror circuit and compare the structure with direct static CMOS circuit.
(10 marks)
00
Q5)
a)
What are the different types of design rules? Draw layout of two input CMOS NAND gate as per lambda based design rules (show units in lambda).
(10 marks)
00
b)
Explain in detail static and dynamic power dissipation. What are the main components which make power dissipation in CMOS circuit.
(5 marks)
00
c)
What is clock skew? Explain clock distribution technique in VLSI system.
(5 marks)
00
Q6) Write short notes on any four:
i)
ESD protection circuit
(5 marks)
00
ii)
4x4 Barrel shifter
(5 marks)
00
c)
Latch up
(5 marks)
00
d)
3-T DRAM
(5 marks)
00
e)
Decoder in memory structure
(5 marks)
00
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