2. Low power design consideration

Static

$P_{ds}=V_{DD}.I_D$

dynamic

$Q=C_oV_{DD}$

$= V_{DD}.Q/t$

$=V_{DD}^2 . C_o.f$

Total average $P= V_{DD}.I_D+ V_{DD}^2.C_o.f$

3. Interconnect scaling

W , t, td = three interconnect parameter

Resistance:

W’=w/s

R=Rs(L/w)

R’=R=Rs=sRs=sr

R’(line)=sr(line)

But l’=l/s

R’(line)= r(line)

Cap:

$c^{'} = E_o [1.15(w^{'}/t_d) + 2.8(t/t_d)^{0.222}]$

C’=C/s

$C’_{line}= C_{line}/S^2$

4. Input and output protection circuit

• CM OS chips must be electrostatic discharge protection circuit at its input

• ESD event is the transfer of charge between two bodies at different potential

• ESD generates High Voltage or high peak current that may damage IC

• $E_{ox} = \frac{V_G}{t_{ox}}$

Oxide thickness in everything electric field are quite large

• A Tox in decreasesEox increase also Vgt increases Eox increases beyond maximum electric field and destroy it completly

• During PSD Hai positive voltage is applied at iPad the D1 and D2 under breakdown and thus prevents resistance drop the voltage level along IP line

Normal ops -D1 and D2 = RB

If i/p voltage increases above Vdd D1 conducts which D2 conducts with Vin decreases ground

5. Cross talks

• Unwanted transfer of signal from 1 place to another through coupling cap is crosstalk

• Consider 2 wires running in parallel

Wire 1 = C1 and V1 and wire 2= C2 and V1

• If isolated Q1=C1V1 and Q2=C2V2

• Since coupled coupling cap must be introduced,

  Q1=C1V1 +CcoupV2

Q2=CcoupV1+CCcoup

Diff

$i_1=dQ_1/dt=C_1dV_1/t+C_{coup} dV_2/dt$

$i_2=dQ_2/dt =C_{coup} dV_1/dt +C_2dV_2/dt$

• When voltage of one line changes i1 and I2 also changes lead to decoration speed health causes crosstalk

• To avoid

• i) To crosstalk increase spacing between wire which decrease Ccoup

• ii) Place ground lines on vdd between signal lines